Abstract: This paper introduces the design of the strain force test system based on TMS320VC33 DSP chip, gives the structural principle block diagram, and designs the interrupt, reset subsystem, storage subsystem and communication subsystem of the test system around DSP. Signal integrity analysis was also performed on the test system. Keywords: test system; DSP; strain force; signal integrity The force between the wheel and the track is an important factor to evaluate the running quality of the vehicle. Whether the force between the wheel and the rail can be accurately and timely can directly affect the calculation of the parameters such as the derailment coefficient of the vehicle. The strain test system is the key link for designing the ground safety monitoring platform for train operation status. The test system developed with DSP chip is aimed at this need. Test system hardware design Overall structure of the system The test system is based on high-speed, high-precision DSP, and constitutes a real-time signal test processing system including analog signal preprocessing, A/D conversion, and D/A conversion. Its principle block diagram is shown in Figure 1. The analog signal output by the strain sensor is preliminarily filtered out by the RC filter network to the high frequency component of the signal, and then converted into a digital signal by A/D conversion. The RC filter network and A/D conversion constitute the forward channel of the test system. The central processing unit is based on the TMS320VC33, a high-precision, high-capacity, wide-power floating-point processor with high parallelism and DMA coprocessor channels. At the same time, the design also set up a 64K & TImes; 32-bit data memory and 512K & TImes; 8-bit program memory, together with the DSP to form the storage system of the entire system. Programmable logic (CPLD) is the hardware control core of the test system. Its main task is to control the A/D conversion and generate the chip select signal of the storage system. Interrupt, reset subsystem design In this test system, the DSP needs to be composed separately to form a system, so the TMS320VC33 is set to the microcomputer mode, and the TMS320VC33 has a program guiding function. When the system is powered on or reset, the TMS320VC33 monitors the status of the four interrupt pins, determines the address of the user program according to the BootLoader program location table, and then runs its own BootLoader program to download the user program to the specified address space. The reset circuit of the system BootLoader is shown in Figure 2. Clock circuit design The clock of TMS320VC33 can be provided by external or on-board oscillator, but the accuracy of external clock is high, stability and easy to use. Therefore, 12MHz external clock CLKMD0 CLKMD1=11 clock is used in this design. The mode, after 5 times internal, produces a system clock of 60 MHz. Bus driver Due to the limited drive capability of the DSP's address bus and data bus, when the load is large, the bus driver needs to be extended to ensure the system can work stably. This design uses TI's wide bus 16-bit bidirectional bus driver SN74LVTH16245, which has high integration and performance. Storage subsystem design The main problem in memory interface design considerations is how to implement the storage subsystem using the EP2ROM+ high-speed RAM configuration. The EP2ROM is used to store the program and initialization data of the test system. When the system is powered up, the TMS320VC33 automatically loads the program and initialization data from the low-speed EP2ROM into the high-speed RAM. After loading, the program runs at full speed in high-speed RAM. The EP2ROM start address of the memory loader and initialization data in the system is 400000h. At the same time, the system also expands 64K high-speed RAM, the starting address is 100000h. In addition, the chip select signal is implemented by the CPLD in the system. For the interface between TMS320VC33 and EP2ROM, the system uses an AM29F040 (512K & TImes; 8) to achieve 8-bit data width program guidance. The address space occupied by EP2ROM is 400000h~47FFFFh. The waiting period inserted when reading the EP2ROM is controlled by software. The program and data of the TMS320VC33 real-time runtime are stored in the fast RAM, so the fast RAM and the TMS320VC33 must implement a zero-wait interface. According to the timing requirements, when the TMS320VC33 operates on a 60MHz clock, the fast RAM access speed must be less than 13ns. The fast RAM used in this test system is IS61LV6416-8T with an access speed of 8ns. Since the data width of the fast RAM is 16 bits, and the data width of the TMS320VC33 is 32 bits, two slices must be used to form a 32-bit data width, and the write enable signal is connected to the decoded write signal, and the output is enabled. The signal is coupled to the decoded read signal. The address space occupied by the fast RAM in the test system is 0x100000~0x110000. Communication subsystem In the strain test system, in order to transfer the processing result of the TMS320VC33 to the sampling signal to the PC for display or further processing, the design uses TI's TL16C550 extended asynchronous communication chip to connect the DSP to the PC to complete the test system. Communication with a PC. In the serial communication between TL16C550 and TMS320VC33, although it can work by query, this will reduce the performance of the system. This design introduces an external interrupt through the RXRDY and TXRDY pins of the TMS320VC33, thus enabling the system to operate in an interrupt mode, ensuring high-speed communication between the TMS320VC33 and the PC. In addition, the test system uses the serial communication interface of the TL16C550 to exchange information with the host PC. At this time, since the RS-232 circuit level is different from the TTL level, it must be level-shifted, and the MAX232A is used in the design to accomplish this function. Programmable Logic Device - Decoding Module The decoding module in the test system is mainly used to implement the DSP to manage the off-chip memory and I/O devices, and to allocate different address spaces to the external memory and I/O devices according to the address signals provided by the DSP. For the test system, the coding mode mainly considers the interface capability of the TMS320VC33. The TMS320VC33 has a total address space of 16M. Uniform addressing does not pose a significant threat to memory capacity. In addition, TMS320VC33 does not have a dedicated I / O command and I / O port bus, so the test system uses a unified encoding, and uses the ABLE language Design the decoding circuit. Test system software design The pros and cons of the test software algorithm are directly related to the performance of the entire test system. The software flow of this test system is shown in Figure 3. The test program first performs the initialization of the entire system. After the system initialization is completed, the system is in the query state, the query completes the new data sampling, and the data sampling program is completed in the interrupt program. When the system completes an A/D conversion, it requests an interrupt to the TMS320VC33. The TMS320VC33 responds to the interrupt, reads the conversion result in the interrupt service routine and sets the flag: EXINT=1, notifying the main program that the sampling is completed. After the main program queries EXINT=1, the data is processed. The processing result is sent to the serial port of the PC through the parallel port of TMS320VC33 and serially converted to the serial port of the PC, and the flag EXINT is set to 0 to start the next round of sampling waiting. Signal integrity analysis and electromagnetic compatibility design Considering the harsh environment in which the system operates, the electromagnetic interference of the track line is relatively strong, so signal integrity and electromagnetic compatibility issues should be considered in the design. Table 1 summarizes the common signal integrity issues and possible causes and solutions in high-speed digital circuits. Power EMI is a major factor affecting the system's immunity to interference. The simple method is to connect a capacitor in parallel with the power supply pin of each chip for power supply filtering. Another factor that affects the system's anti-jamming capability is the quality of the traces on the board. The inductance of the printed conductor should be minimized and the conductors should be as short and thick as possible. At the same time, attention should be paid to suppressing crosstalk between printed circuit board conductors and avoiding electromagnetic radiation generated when high-frequency signals pass through the printed wiring. In addition, care must be taken to properly arrange the power supply ground. Conclusion The DSP-based train strain test system proposed and designed in this paper effectively solves the technical problems in practical engineering applications, and considers the signal integrity analysis and anti-electromagnetic interference capability of the test system. Thus providing a good reference solution for data acquisition and processing.
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The interrupt and reset subsystem not only acts as a system reset, but is also used to determine the location of the system application. The DSP loads the application and runs according to this system.
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